Fabrication of a newly-designed integrated circuit (“IC”) involves preparation of silicon substrate wafers, generation of masks, doping of the silicon substrate, deposition of metal layers, and so on. The IC typically has many physical layers on the substrate with various individual electronic components, such as resistors, capacitors, diodes, and transistors, collectively forming one or more electrical circuits. The metal layers, which may be aluminum, copper, or other conductive material, provide the interconnection mesh between the various individual electronic components to form integrated electrical circuits. Vias formed of electrically conductive material provide communication pathways between various metal layers. Contacts provide communication links between metal layers and individual electronic components embedded in the silicon substrate.
Unfortunately, a new IC of any complexity rarely works as expected when first fabricated. Normally, some defects in the operation of the IC are discovered during testing. Also, some functions of the IC may operate properly under limited conditions, but fail when operated across a full range of temperature and voltage in which the IC is expected to perform. Once the IC has been tested, the designer may change the design, initiate the manufacture of a second prototype IC via the lengthy process described above, and then test the new IC once again. However, no guarantee exists that the design changes will correct the problems previously encountered, or that all of the problems in the previous version of the IC have been discovered. It is also possible that a design will need to be altered for some other reason.
Charged particle beam systems, such as focused ion beam (“FIB”) systems and electron beam (“e-beam”) systems, laser based systems, and other integrated circuit operation platforms have found many applications in various areas of science and industry. Particularly in the semiconductor industry, charged particle beam systems are used for integrated circuit edits, probe point creation, failure analysis, and numerous other applications. More generally, servicing platforms may be used for testing, analyzing, editing, and/or repairing an IC. For example, charged particle beam systems may be used to edit a circuit (“circuit editing”) in order to test design charges and thereby avoid some or all of the expense and time of testing design changes through fabrication. Particularly, a FIB tool typically includes a particle beam production column designed to precisely focus an ion beam on the IC at the place intended for the desired intervention. Such a column typically comprises a source of ions, such as Ga+ (Gallium), produced from liquid metal. The Ga+ is used to form the ion beam, which is focused on the IC by a focusing device comprising a certain number of electrodes operating at determined potentials so as to form an electrostatic lens system. Other types of charged particle beam systems deploy other arrangements to produce charged particle beams capable of various types of circuit edits and operations generally. Further, laser-based systems deploy various types of lasers for purposes of laser based circuit editing.
As mentioned above, IC manufacturers sometimes employ a FIB system to edit the prototype IC, thereby altering the connections and other electronic structures of the IC. Circuit editing involves employing an ion beam to remove and deposit material in an IC with precision. Removal of material, or milling, may be achieved through a process sometimes referred to as sputtering. Addition or deposition of material, such as a conductor, may be achieved through a process sometimes referred to as ion-induced deposition. Through removal and deposit of material, electrical connections may be severed or added, which allows designers to implement and test design modifications without repeating the wafer fabrication process.
When a charged particle beam or laser operation is planned, the problem arises of selecting the area of the circuit where each step is to be carried out. Typically, there are many theoretical possibilities for executing each step, all equivalent with respect to the electrical circuit. For example, an equipotential branch can be cut at any point, an electrical measurement can be made at any point of a branch, and a deposition can be carried out to form a connection between two branches between any two points on these branches. However, while theoretically equivalent or the same, the many alternative locations for any circuit operation are not the same or equivalent in terms of practicality. First, the servicing area must be accessible to the servicing tool from the access surface. For example, cutting a metal connection hidden under a transistor configuration would require the damage or destruction of the transistor to reach the metal connection. Second, the difficulty of execution is not always the same. For example, it is more difficult to perform a circuit operation in an area with densely arranged circuit elements than in an area of less densely arranged elements. Third, the duration of the work can vary considerably. The duration depends on various factors including the depth of the layer on which the work is done (in other words, the distance from the access surface) and the difficulty of accessing the servicing area in question with the tool. In the case of deposition, the duration also depends on the length of the track that is deposited.
For any modern IC, descriptive data is provided to identify, in each layer of a circuit, a number of polygons, each formed from a characteristic material (metal, polysilicon, etc.), by which the IC is fabricated. The IC descriptive data is often referred to as “layout” data. Further data representing the logical or electrical layout of the circuit is also typically provided, which may be displayed in schematic form.
Conventionally, determining the proper location for a circuit operation is an iterative manual process. First, a designer may request a change in the schematic for some reason. There are numerous possible reasons for a requesting a design change, such as identification of a design error, identification of a process-design interaction that may impact yield, identification of an IC functionality error during testing, customer changes to an IC specification, etc. The designer request is often made at the schematic or logic level. So, for example, the designer requests that an output signal from a logic block be connected to another logic block, when the connection is not currently present. There is currently no standard form for the designer to make a request for a circuit edit. As such, the request may be made by way of email, sketches, memorandum, marked-up RTL or netlist print-outs, and the list goes on.
From the schematic request, someone must check the physical layout and attempt to ascertain where in the layout a change should be made to meet the schematic request. Then, the circuit editor, e.g., the person that runs the FIB tool, double checks the requested layout change. After determining a location in the layout to make a change, the decision is returned to the front-end design person for approval.